Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Embedded tutorial: formal equivalence checking between system-level models and RTL
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Microprocessors & Microsystems
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In this paper, we propose a novel approach to verify equivalence of C-based system level description versus Register Transfer Level (RTL) model by looking for merge points as early as possible to reduce the size of equivalence checking problems. We tackle exponential path enumeration problem by identifying merge points as well as equivalent nodes automatically. It will describe a hybrid bit- and word-level representation called Linear Taylor Expansion Diagram (LTED) [1] which can be used to check the equivalence of two descriptions in different levels of abstractions. This representation not only has a compact and canonical form, but also is close to high-level descriptions so that it can be utilized as a formal model for many EDA applications such as synthesis. It will then show how this leads to more effective use of LTED to verify equivalence of two descriptions in different levels of abstractions. We use LTED package to successfully verify some industrial circuits. In order to show that our approach is applicable to industrial designs, we apply it to 64- point Fast Fourier Transform and Viterbi algorithms that are the most computationally intensive parts of a communication system.