Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
RTL c-based methodology for designing and verifying a multi-threaded processor
Proceedings of the 39th annual Design Automation Conference
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Higher-Level Specification and Verification with BDDs
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Applications of symbolic simulation to the formal verification of microprocessors
Applications of symbolic simulation to the formal verification of microprocessors
Cutpoints for formal equivalence verification of embedded software
Proceedings of the 5th ACM international conference on Embedded software
An equivalence checking methodology for hardware oriented C-based specifications
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Hardware verification using ANSI-C programs as a reference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Embedded tutorial: formal equivalence checking between system-level models and RTL
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constructing efficient formal models from high-level descriptions using symbolic simulation
International Journal of Parallel Programming
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microprocessors & Microsystems
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Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intended for synthesis. Thus, equivalence verification between the high-level software functional model and the RTL is needed. The typical approach is to convert the high-level software into RTL or gate-level hardware, via software path enumeration, symbolic execution, or high-level synthesis techniques, and then use hardware combinational equivalence checking. The principle contribution of this paper is to introduce cutpoints --- as in gate-level combinational equivalence verification --- early during the analysis of the software model, thereby avoiding exponential path enumeration and the potential logical complexity blow-up of merging execution paths that can occur in the usual approach. The method is conservative, but in our experiments, we did not encounter spurious counterexamples, and the method showed large improvements in runtime and memory usage on a family of IA-32 subset instruction length decoders, an industry-suggested challenge problem.