Functional Validation of System Level Static Scheduling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cutpoints for formal equivalence verification of embedded software
Proceedings of the 5th ACM international conference on Embedded software
Partitioned model checking from software specifications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Engineering changes in field modifiable architectures
Formal methods and models for system design
Proceedings of the 43rd annual Design Automation Conference
Verification of system level model transformations
International Journal of Parallel Programming
Formal equivalence checking for loop optimization in C programs without unrolling
ACST'07 Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
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Verification to validate designs is one of the important tasks in VLSI design flow. Due to the great advances in integration, verification for whole designs is getting more and more difficult. To solve this problem in early stages of design flows, we suggest a formal equivalence checking method for given two C-based hardware oriented specifications (C descriptions). To verify large C descriptions efficiently, we use textual differences in the two C descriptions and verify them in terms, of symbolic simulation. We believe that our approach will be useful where two specifications to be verified are very close, which is a very common situation in practical designs.