Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation

Authors:
Kong Woei Susanto;Tim Todman;Jose Gabriel Coutinho;Wayne Luk
Affiliations:
Department of Computing, Imperial College London, London, United Kingdom SW7 2BZ;Department of Computing, Imperial College London, London, United Kingdom SW7 2BZ;Department of Computing, Imperial College London, London, United Kingdom SW7 2BZ;Department of Computing, Imperial College London, London, United Kingdom SW7 2BZ
Venue:
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
Year:
2009

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Abstract

Design optimization exploration is a key element in finding an optimal resource utilization. The exploration process applies optimizations iteratively; after applying each optimization, the result has to be validated. The research challenge for formal verification is to develop an efficient design validation flow and increase the quality of the validation. In this paper, we propose an automated validation flow to check the functional equivalence of the source design and its optimized version. This approach is based on a symbolic simulation technique to obtain the design properties and automatically check them using an equivalence checker. The novelty of this approach includes the use of model simplification techniques, such as if-conversion and loop-conversion, and state encoding to ease validation analysis.