Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
A computational logic handbook
A computational logic handbook
Analysis of discrete event coordination
REX workshop Proceedings on Stepwise refinement of distributed systems: models, formalisms, correctness
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
A Novel EDA Tool for VLSI Test Vectors Management
Journal of Electronic Testing: Theory and Applications
Processor Description Languages
Processor Description Languages
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
| Hi-index | 0.00 |
CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve.