Minimal cost set covering using probabilistic methods
SAC '93 Proceedings of the 1993 ACM/SIGAPP symposium on Applied computing: states of the art and practice
Design challenges for 0.1um and beyond: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Introduction to VLSI Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A parallel genetic algorithm to solve the set-covering problem
Computers and Operations Research
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Optimal Vector Selection for Low Power BIST
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Branch-and-Bound Algorithms for the Test Cover Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
Current status and future trend on CAD tools for VLSI testing
ATS '00 Proceedings of the 9th Asian Test Symposium
Behavioral-level test vector generation for system-on-chip designs
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Toward Design Technology in 2020: Trends, Issues, and Challenges
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A portable ATPG tool for parallel and distributed systems
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Computer
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
ATS '04 Proceedings of the 13th Asian Test Symposium
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In today's semiconductor industry, where time-to-profit is a critical factor to remain competitive, missing the tight market window might have serious implications including the risk of product cancellation. This places severe pressure on every aspect related to the design and the verification of semiconductor chips to get the design ready for manufacturing in the shortest time possible. To avoid the need for costly corrective steps and silicon re-spins during post-silicon verification, thorough pre-silicon verification is essential to catch any design fault and estimate the design overall reliability before the design is manufactured. This paper presents a novel EDA tool that helps the verification team improve the verification process in several ways. It can be used to generate useful statistics regarding the complexity and the coverage of the created test vectors. Experimental results prove that the verification team can successfully use the proposed tool to set their target coverage and intelligently select the set of test vectors that achieves that target using the minimum number of computing cycles.