A Novel EDA Tool for VLSI Test Vectors Management
Journal of Electronic Testing: Theory and Applications
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The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATEýs (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.