A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting short circuit power from timing models
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A Novel EDA Tool for VLSI Test Vectors Management
Journal of Electronic Testing: Theory and Applications
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
Journal of Signal Processing Systems
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