Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Array Solution for Testing Power and Testing Time
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
Evaluation of heuristic techniques for test vector ordering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Novel EDA Tool for VLSI Test Vectors Management
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application the circuits are subject to an activity higher than the normal one: the extra power consumption due to test application may thus give rise to severe hazards to the circuit reliability. Moreover, it can dramatically shorten the battery life when periodic testing of battery-powered systems is considered. In this paper we propose a low power BIST architecture devised for full scan testing of sequential circuits. Experimental results show that our approach can achieve an average power reduction ranging from 37% to 89% without affecting the quality of the test. The new architecture can be easily integrated into an existing design flow and is barely invasive with respect to the original BIST circuit.