Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Multilevel Design Validation in a Secure Embedded System
IEEE Transactions on Computers
Processor Description Languages
Processor Description Languages
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A major challenge in today's functional verification is the lack of a formal specification with which to compare the RTL model. The authors propose a novel top-down verification approach that allows specification of a design above the RTL. From this specification, it is possible to automatically generate assertion models and RTL reference models. The authors also demonstrate that symbolic simulation and equivalence checking can be applied to verify an RTL design against its specification.