Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Journal of Electronic Testing: Theory and Applications
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Design for Verification at the Register Transfer Level
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Formal Methods in System Design
Error Diagnosis in Equivalence Checking of High Performance Microprocessors
Electronic Notes in Theoretical Computer Science (ENTCS)
Processor Description Languages
Processor Description Languages
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Word level feature discovery to enhance quality of assertion mining
Proceedings of the International Conference on Computer-Aided Design
Generating concise assertions with complete coverage
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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For verifying complex sequen tialbloc ks such as microprocessor embedded arrays, the formal method of symbolic trajectory ev aluation (STE) has achieved great success in the past [[3], [5], [6]]. P ast STE methodology for arrays requires manual creation of “assertions” to which both the RTL view and the actual design should be equivalent. In this paper, w e describe a novel method to automate the assertion creation process which improves the efficiency and the quality of array verification. Encouraging results on recent P owerPC arrays will be presented.