Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Symbolic exploration of large circuits with enhanced forward/backward traversals
EURO-DAC '94 Proceedings of the conference on European design automation
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
DAC '98 Proceedings of the 35th annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Model checking
Efficient Simulation of Formal Processor Models
Formal Methods in System Design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Algorithms and Data Structures in VLSI Design
Algorithms and Data Structures in VLSI Design
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Floating Point Trigonometric Functions
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of the Alpha 21364 Network Protocol
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Reachability Programming in HOL98 Using BDDs
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Mathematically Precise Two-Level Formal Hardware Verification Methodology*
A Mathematically Precise Two-Level Formal Hardware Verification Methodology*
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Functional validation of hardware designs is a major challenge for circuit design companies. Post-delivery software problems can be addressed by subsequent software releases; however, fixing hardware bugs in any shipped product is expensive. Simulation remains the dominate functional validation method, but in the last decade, formal verification (FV) has emerged as an important complementary method. We describe basic FV methods: theorem proving, model checking, and equivalence checking with some illustrations from their applications to Alpha microprocessor designs. The last one is described in detail. Although theoretically, FV can provide much more complete verification coverage than simulation, our ability to apply FV is limited due to capacity limits of existing FV tools and the availability of trained personnel. The application of FV to industrial designs is an active research area with huge opportunities for academic and industrial researchers.