Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
ACM Transactions on Computer Systems (TOCS)
EURO-DAC '92 Proceedings of the conference on European design automation
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Integrating formal verification methods with a conventional project design flow
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
The future of logic synthesis and verification
Logic Synthesis and Verification
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Symbolic representation with ordered function templates
Proceedings of the 40th annual Design Automation Conference
On the non-termination of MDG-based abstract state enumeration
Theoretical Computer Science
Formal Verification of Digital Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Automated Analysis of Reo Circuits using Symbolic Execution
Electronic Notes in Theoretical Computer Science (ENTCS)
Symbolic execution of Reo circuits using constraint automata
Science of Computer Programming
An integrated approach to verifying large circuits: a case study
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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