Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking and modular verification
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Benchmark-Circuits for Hardware-Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Combining Model Checking and Theorem Proving to Verify Parallel Processes
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
VHDL Description and Formal Verification of Systolic Multipliers
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Model Checking Partially Ordered State Spaces
Model Checking Partially Ordered State Spaces
Verification of Benchmarks 17 and 22 of the IFIP WG10.5 Benchmark Circuit Suite
Verification of Benchmarks 17 and 22 of the IFIP WG10.5 Benchmark Circuit Suite
Compositional model checking of partially ordered state spaces
Compositional model checking of partially ordered state spaces
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A symbolic core approach to the formal verification of integrated mixed-mode applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Through the use of compositionality and abstraction, it is possible to extend automatic model checking techniques so that large circuits can be verified. This paper presents a case study verification of Benchmark 22 of the IFIP WG10.5 Benchmark Suite for Hardware Verification (a systolic array multiplier containing 115 000 gates). Both the timing and functionality of the circuit are verified (a significant error was discovered in the original benchmark). This illustrates that an appropriate logical framework can support an efficient, integrated tool for verification that incorporates a number of different verification techniques. A specialised theorem prover implements a compositional theory based on symbolic trajectory evaluation (STE). STE, an efficient model checking technique that can support large state spaces because of its natural and easily used method of abstraction, provides the underlying computational engine. The rest of the compositional theory allows a human verifier to use knowledge of the structure of the circuit to overcome some of the computational limitations of model checking. Using STE with its compositional theory, large circuits can be verified in detail using reasonable computational resources.