Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
Formal Verification and Hardware Design with Statecharts
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
BDD-Nodes Can Be More Expressive
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Minimization of multiway decision graphs for RTL verification by stochastic optimization
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
An integrated approach to verifying large circuits: a case study
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
| Hi-index | 0.00 |