Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
A Mathematically Precise Two-Level Formal Hardware Verification Methodology*
A Mathematically Precise Two-Level Formal Hardware Verification Methodology*
An Introduction to Formal Hardware Verification
An Introduction to Formal Hardware Verification
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal hardware verification by integrating HOL and MDG
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Importing MDG Verification Results into HOL
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Combining Theorem Proving and Model Checking through Symbolic Analysis
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Xs are for Trajectory Evaluation, Booleans are for Theorem Proving
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hierarchical Verification Using an MDG-HOL Hybrid Tool
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Applications of Hierarchical Verification in Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Reformulate Dynamic Properties during B Refinement and Forget Variants and Loop Invariants
ZB '00 Proceedings of the First International Conference of B and Z Users on Formal Specification and Development in Z and B
Formally Linking MDG and HOL Based on a Verified MDG System
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Providing a formal linkage between MDG and HOL
Formal Methods in System Design
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Integration of a software model checker into isabelle
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
An integrated approach to verifying large circuits: a case study
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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