Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Comparing HOL and MDG: a case study on the verification of an ATM switch fabric
Nordic Journal of Computing
Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
Experiments in Theorem Proving and Model Checking for Protocol Verification
FME '96 Proceedings of the Third International Symposium of Formal Methods Europe on Industrial Benefit and Advances in Formal Methods
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical Verification Using an MDG-HOL Hybrid Tool
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formally Linking MDG and HOL Based on a Verified MDG System
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
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Formal hardware verification systems can be split into two categories: theorem proving systems and automatic finite state machine based systems. Each approach has its own complementary advantages and disadvantages. In this paper, we consider the combination of two such systems: HOL (a theorem proving system) and MDG (an automatic system). As HOL hardware verification proofs are based on the hierarchical structure of the design, submodules can be verified using other systems such as MDG. However, the results of MDG are not in the appropriate form for this. We have proved a set of theorems that express how results proved using MDG can be converted into the form used in traditional HOL hardware verification.