Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Fairisle: an ATM network for the local area
SIGCOMM '91 Proceedings of the conference on Communications architecture & protocols
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
On the comparison of HOL and Boyer-Moore for formal hardware verification
Formal Methods in System Design
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic Model Checking
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Formal Hardware Verification - Methods and Systems in Comparison
Formal Hardware Verification - Methods and Systems in Comparison
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A case study on design for provability
ICECCS '95 Proceedings of the 1st International Conference on Engineering of Complex Computer Systems
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Improving hardware designs whilst simplifying their proof
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Indeed: Interactive Deduction on Horn Clause Theories
IBERAMIA 2002 Proceedings of the 8th Ibero-American Conference on AI: Advances in Artificial Intelligence
Importing MDG Verification Results into HOL
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
| Hi-index | 0.00 |
Interactive formal proof and automated verification based on decision graphs are two contrasting formal hardware verification techniques. In this paper, we compare these two approaches. In particular, we consider HOL and MDG. The former is an interactive theorem-proving system based on higher-order logic, while the latter is an automatic system based on Multiway Decision Graphs. As the basis for our comparison we have used both systems to independently verify a fabricated ATM communications chip, the Fairisle 4 by 4 switch fabric.