ATM switch design by high-level modeling, formal verification and high-level synthesi
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Comparing HOL and MDG: a case study on the verification of an ATM switch fabric
Nordic Journal of Computing
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Automatic Verification of Combinatorial and Pipelined FFT
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Hardware Verification Using Co-induction in COQ
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
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In this paper we present our results on formally verifying the implementation of an Asynchronous Transfer Mode (ATM) network switching fabric using a new class of decision graphs, called Multiway Decision Graphs (MDG). The design we consider is in use for real applications in the Cambridge Fairisle network. We produced the description of the hardware implementation at different levels of abstraction. We then performed the verification of an abstract description model against the description of the gate-level implementation. Using this abstract model, we accomplished the verification of specific properties that reflect the behavior of the Fairisle ATM switch fabric.