Automatic Verification of Combinatorial and Pipelined FFT

  • Authors:

  • Per Bjesse

  • Affiliations:

  • -

  • Venue:
  • CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
  • Year:
  • 1999

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Abstract

We describe how three hardware components (two combinational and one pipelined) for computing the Fast Fourier Transform have been proved equivalent using an automatic combination of symbolic simulation, rewriting techniques, induction and theorem proving. We also give some advice on how to verify circuits operating on complex data, and present a general purpose proof strategy for equivalence checking between combinational and pipelined circuits.