Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

Authors:
Miroslav N. Velev;Randal E. Bryant
Affiliations:
-;-
Venue:
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Year:
1998

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Abstract

We present a way to abstract functional units in symbolic simulation of actual circuits, thus achieving the effect of uninterpreted functions at the bit-level. Additionally, we propose an efficient encoding technique that can be used to represent uninterpreted symbols with BDDs, while allowing these symbols to be propagated by simulation with a conventional bit-level symbolic simulator. Our abstraction and encoding techniques result in an automatic symmetry reduction and allow the control and forwarding logic of the actual circuit to be used unmodified. The abstraction method builds on the behavioral Efficient Memory Model [18][19] and its capability to dynamically introduce consistent initial state, which is identical for two simulation sequences. We apply the abstraction and encoding ideas on the verification of pipelined microprocessors by correspondence checking, where a pipelined microprocessor is compared against a non-pipelined specification.