Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation

Authors:
Randal E. Bryant;Miroslav N. Velev
Affiliations:
-;-
Venue:
ASIAN '97 Proceedings of the Third Asian Computing Science Conference on Advances in Computing Science
Year:
1997

Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor

Formal Methods in System Design
Memory modeling in ESL-RTL equivalence checking

Proceedings of the 44th annual Design Automation Conference
EPR-based bounded model checking at word level

IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning

Hi-index	0.00