Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation: An ACL2 Approach
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation of the JEM1 Microprocessor
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
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Formal verification tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of memory operations. During symbolic simulation, relationships between memory operations are automatically detected while addresses and the memory states are given symbolically to summarize many test-vectors. The integration of the technique in the equivalence checker is demonstrated by example designs.