Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
State reduction using reversible rules
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Applied Boolean Equivalence Verification and RTL Static Sign-Off
IEEE Design & Test
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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An approach for interpreted sequential verification at different levels of abstraction by symbolic simulation is proposed. The equivalence checker has been used in previous work to compare two designs at rt-level.We describe in this paper the automatic verification of gate-level results of a commercial synthesis tool against a behavioral specification at rt-level. The symbolic simulator has to cope with different numbers of control steps since the descriptions are not cycle equivalent. The state explosion problem of previous approaches relying on state traversal is avoided.The simulator uses a library of different equivalence detection techniques which are surveyed with main emphasis on the new techniques required at gate-level. Cooperation of those techniques and good debugging support are possible by notifying detected relationships at equivalence classes rather than to manipulate symbolic terms.