Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Introduction to algorithms
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A methodology for formal hardware verification, with application to microprocessors
A methodology for formal hardware verification, with application to microprocessors
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal Modeling and Verification of Microprocessors
IEEE Transactions on Computers
Efficiency of a Good But Not Linear Set Union Algorithm
Journal of the ACM (JACM)
A Practical Decision Procedure for Arithmetic with Function Symbols
Journal of the ACM (JACM)
Fast Decision Procedures Based on Congruence Closure
Journal of the ACM (JACM)
Simplification by Cooperating Decision Procedures
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal Verification of a Pipelined Microprocessor
IEEE Software
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scalable formal verification methodology for pipelined microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Verifying correct pipeline implementation for microprocessors
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Specification and verification of pipelining in the ARM2 RISC microprocessor
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Computational Logic (TOCL)
Formal Verification of Out-of-Order Execution with Incremental Flushing
Formal Methods in System Design
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Functional Evaluation
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of Explicitly Parallel Microprocessors
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Efficient Term-ITE Conversion for Satisfiability Modulo Theories
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
An interpolation method for CLP traversal
CP'09 Proceedings of the 15th international conference on Principles and practice of constraint programming
From propositional satisfiability to satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
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We describe an efficient validity checker for the quantifier-free logic of equality with uninterpreted functions. This logic is well suited for verifying microprocessor control circuitry since it allows the abstraction of datapath values and operations. Our validity checker uses special data structures to speed up case splitting, and powerful heuristics to reduce the number of case splits needed. In addition, we present experimental results and show that this implementation has enabled the automatic verification of an actual high-level microprocessor description.