Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Statecharts: A visual formalism for complex systems
Science of Computer Programming
The notion of proof in hardware verification
Journal of Automated Reasoning
Mechanizing programming logics in higher order logic
Current trends in hardware verification and automated theorem proving
ACM Transactions on Software Engineering and Methodology (TOSEM)
Tutorial notes on partial evaluation
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Requirements Specification for Process-Control Systems
IEEE Transactions on Software Engineering
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Completeness and Consistency in Hierarchical State-Based Requirements
IEEE Transactions on Software Engineering - Special issue: best papers of the 17th International Conference on Software Engineering (ICSE-17)
Automated consistency checking of requirements specifications
ACM Transactions on Software Engineering and Methodology (TOSEM)
Checking properties of safety critical specifications using efficient decision procedures
FMSP '98 Proceedings of the second workshop on Formal methods in software practice
Proving Theorems about LISP Functions
Journal of the ACM (JACM)
Efficient compilation of lazy evaluation
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
State-Based Model Checking of Event-Driven System Requirements
IEEE Transactions on Software Engineering
Experience with Embedding Hardware Description Languages in HOL
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
FORTE X / PSTV XVII '97 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE X) and Protocol Specification, Testing and Verification (PSTV XVII)
Symbolic Simulation of the JEM1 Microprocessor
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic
HOL'92 Proceedings of the IFIP TC10/WG10.2 Workshop on Higher Order Logic Theorem Proving and its Applications
A Formalisation of the VHDL Simulation Cycle
HOL'92 Proceedings of the IFIP TC10/WG10.2 Workshop on Higher Order Logic Theorem Proving and its Applications
The Semantics of Statecharts in HOL
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
Toward a Super Duper Hardware Tactic
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
S: A Machine Readable Specification Notation based on Higher Order Logic
Proceedings of the 7th International Workshop on Higher Order Logic Theorem Proving and Its Applications
Executing Formal Specifications by Translation to Higher Order Logic Programming
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Microprocessor Specification in Hawk
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
The formal verification of generic interpreters
The formal verification of generic interpreters
A framework for multinotation, model-orientated requirements analysis
A framework for multinotation, model-orientated requirements analysis
The Implementation of Functional Programming Languages (Prentice-Hall International Series in Computer Science)
Symbolic Simulation of Microprocessor Models using Type Classes in Haskell
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Mapping Template Semantics to SMV
Proceedings of the 19th IEEE international conference on Automated software engineering
Prescriptive semantics for big-step modelling languages
FASE'10 Proceedings of the 13th international conference on Fundamental Approaches to Software Engineering
Code generation for a family of executable modelling notations
Software and Systems Modeling (SoSyM)
Model translations among big-step modeling languages
Proceedings of the 34th International Conference on Software Engineering
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Symbolic functional evaluation (SFE) is the extension of an algorithm for executing functional programs to evaluate expressions in higher-order logic. SFE carries out the logical transformations of expanding definitions, beta-reduction, and simplification of built-in constants in the presence of quantifiers and uninterpreted constants. We illustrate the use of symbolic functional evaluation as a "universal translator" for linking notations embedded in higher-order logic directly with automated analysis without using a theorem prover. SFE includes general criteria for when to stop evaluation of arguments to uninterpreted functions based on the type of analysis to be performed. SFE allows both a novice user and a theorem-proving expert to work on exactly the same specification. SFE could also be implemented in a theorem prover such as HOL as a powerful evaluation tactic for large expression.