A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal Methods in System Design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic Functional Evaluation
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Mechanization Of Real-Time Linear Csp With Higher Order Logic
Fundamenta Informaticae
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