ACM SIGPLAN Notices
Why functional programming matters
The Computer Journal - Special issue on Lazy functional programming
ACM Transactions on Computer Systems (TOCS)
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification of pipeline conflicts in RISC processors
EURO-DAC '94 Proceedings of the conference on European design automation
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A scalable formal verification methodology for pipelined microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Verifying correct pipeline implementation for microprocessors
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
A Practical Methodology for the Formal Verification of RISC Processors
Formal Methods in System Design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On embedding a microarchitectural design language within Haskell
Proceedings of the fourth ACM SIGPLAN international conference on Functional programming
Scalable hybrid verification of complex microprocessors
Proceedings of the 38th annual Design Automation Conference
Specification and Validation of Control-Intensive IC's in hopCP
IEEE Transactions on Software Engineering
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
An Object-Oriented Framework for the Formal Verification of Processors
ECOOP '95 Proceedings of the 9th European Conference on Object-Oriented Programming
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Systematic Formal Verification of Interpreters
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A Practical Methodology for Verifying Pipelined Microarchitectures
IEEE Design & Test
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Automatic verification of external interrupt behaviors for microprocessor design
Proceedings of the 44th annual Design Automation Conference
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail.