ACM Transactions on Programming Languages and Systems (TOPLAS)
Conception, evolution, and application of functional programming languages
ACM Computing Surveys (CSUR)
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Communications of the ACM - Special issue on simulation
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Transactions of the Society for Computer Simulation International
Current trends in hardware verification and automated theorem proving
Current trends in hardware verification and automated theorem proving
Correctness properties of the Viper block model: the second level
Current trends in hardware verification and automated theorem proving
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DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp
IEEE Transactions on Computers
An integrated framework for high-level synthesis of self-timed circuits
An integrated framework for high-level synthesis of self-timed circuits
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ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Validation, Verification, and Testing of Computer Software
ACM Computing Surveys (CSUR)
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IEEE Design & Test
IEEE Software
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IEEE Software
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ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Formal Specification and Verification Framework for Time Warp-Based Parallel Simulation
IEEE Transactions on Software Engineering
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The use of formal methods in hardware design improves the quality of designs in many ways: it promotes better understanding of the design; it permits systematic design refinement through the discovery of invariants; and it allows design verification (informal or formal). In this paper we illustrate the use of formal methods in the design of a custom hardware system called the “Rollback Chip” (RBC), conducted using a simple hardware design description language called “HOP”. An informal specification of the requirements of the RBC is first given, followed by a behavioral description of the RBC stating its desired behavior. The behavioral description is refined into progressively more efficient designs, terminating in a structural description. Key refinement steps are based on system invariants that are discovered during the design, and proved correct during design verification. The first step in design verification is to apply a program called PARCOMP to derive a behavioral description from the structural description of the RBC. The derived behavior is then compared against the desired behavior using equational verification techniques. This work demonstrates that formal methods can be fruitfully applied to a nontrivial hardware design. It also illustrates the particular advantages of our approach based on HOP and PARCOMP. Last, but not the least, it formally verifies the RBC mechanism itself.