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IBM Journal of Research and Development
Microprocessor design verification
Journal of Automated Reasoning
The SECD microprocessor: a verification case study
The SECD microprocessor: a verification case study
A formal HDL and its use in the FM9001 verification
Mechanized reasoning and hardware design
Higher order logic and hardware verification
Higher order logic and hardware verification
FM8501: a verified microprocessor
FM8501: a verified microprocessor
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
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Algebraic models of microprocessors: the correctness and verification of a simple computer
MDS '95 Proceedings of the second international conference on Mathematics of dependable systems II
Formal Verification of a Pipelined Microprocessor
IEEE Software
Towards an Algebraic Specification of the Java Virtual Machine
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
Verification of a Pipelined Microprocessor Using Clio
Workshop on Hardware Specification, Verification and Synthesis: Mathematical Aspects
A Tutorial on Using PVS for Hardware Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
An Algebraic Model of Correctness for Superscalar Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Automatic Generation of Invariants in Processor Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Inverting the Abstraction Mapping: A Methodology for Hardware Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Mechanically Checking a Lemma Used in an Automatic Verification Tool
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Report on the UCD Microcoded Viper Verification Project
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
A Theory of Generic Interpreters
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Algebraic Models and the Correctness of Microprocessors
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Correctness Model for Pipelined Multiprocessors
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
DDD-FM9001: Derivation of a Verified Microprocessor
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Systematic Formal Verification of Interpreters
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
Design of a Computer—The Control Data 6600
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Instruction Issue Logic in Pipelined Supercomputers
IEEE Transactions on Computers
Parallel operation in the control data 6600
AFIPS '64 (Fall, part II) Proceedings of the October 27-29, 1964, fall joint computer conference, part II: very high speed computer systems
The IBM system/360 model 91: machine philosophy and instruction-handling
IBM Journal of Research and Development
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
Towards an Algebraic Specification of the Java Virtual Machine
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
Hierarchies of Spatially Extended Systems and Synchronous Concurrent Algorithms
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verifying a Simple Pipelined Microprocessor Using Maude
WADT '01 Selected papers from the 15th International Workshop on Recent Trends in Algebraic Development Techniques
Algebraic models of simultaneous multithreaded and multi-core processors
CALCO'07 Proceedings of the 2nd international conference on Algebra and coalgebra in computer science
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We extend a set of algebraic tools for representing microprocessors to model superscalar microprocessor implementations, and apply them to a case study. We develop existing correctness models to accommodate the more advanced timing relationships of superscalar processors, and consider formal verication. We illustrate our tools and techniques with an in-depth treatment of an example superscalar implementation. We use clocks to divide time into (not necessarily equal) segments, defined by the natural timing of the computational process of a device. We formally relate clocks by surjective, monotonic maps called retimings. In the case of superscalar microprocessors, the normal relationship between 'architectural time' and 'implementation time' is complicated by the fact that events that are distinct in time at the architectural level can occur simultaneously at the implementation level.