Planning a computer system: Project Stretch
Planning a computer system: Project Stretch
A Simulation Study of Decoupled Architecture Computers
IEEE Transactions on Computers
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
Microprocessors - 10 Years Back, 10 Years Ahead
Informatics - 10 Years Back. 10 Years Ahead.
Performance enhancement of SISD processors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Register File Design Considerations in Dynamically Scheduled Processors
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Register pointer architecture for efficient embedded processors
Proceedings of the conference on Design, automation and test in Europe
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
The Degradation in Memory Utilization Due to Dependencies
IEEE Transactions on Computers
Instruction Issue Logic in Pipelined Supercomputers
IEEE Transactions on Computers
Scheduling Trees in Parallel/Pipelined Processing Environments
IEEE Transactions on Computers
The Inhibition of Potential Parallelism by Conditional Jumps
IEEE Transactions on Computers
The Modeling and Design of Multiple Function-Unit Processors
IEEE Transactions on Computers
A Comparison of Some Theoretical Models of Parallel Computation
IEEE Transactions on Computers
LPA: a first approach to the loop processor architecture
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
An Instruction Fetch Unit for a High-Performance Personal Computer
IEEE Transactions on Computers
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
The challenges of massive on-chip concurrency
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
RDIP: return-address-stack directed instruction prefetching
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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The System/360 Model 91 central processing unit provides internal computational performance oneto two orders of magnitude greater than that of the IBM 7090 Data Processing Systemt hrough a combination of advancements in machine organization, circuit design, and hardware packaging. The circuits employed will switch at speeds of less than 3 nsec, and the circuit environment is such that delay is approximately 5 nsec per circuit level. Organizationally, primary emphasis is placed on (1) alleviating the disparity between storage time and circuit speed, and (2) the development of high speed floating-point arithmetic algorithms. This paper deals mainly with item (1) of the organization. A design is described which improves the ratio of storage bandwidth and access time to cycle time through the use of storage interleaving and CPU buffer registers. It is shown that history recording (the retention of complete instruction loops in the CPU) reduces the need to exercise storage, and that sophisticated employment of buffering techniques has reducedt he effective access time. The system is organized so that execution hardware is separated fromth e instruction unit; the resulting smaller, semiautonomous "packages" improve intra-area communication.