LPA: a first approach to the loop processor architecture

Authors:
Alejandro García;Oliverio J. Santana;Enrique Fernández;Pedro Medina;Mateo Valero
Affiliations:
Universitat Politècnica de Catalunya, Spain;Universidad de Las Palmas de Gran Canaria, Spain;Universidad de Las Palmas de Gran Canaria, Spain;Universidad de Las Palmas de Gran Canaria, Spain;Universitat Politècnica de Catalunya, Spain and Barcelona Supercomputing Center, Spain
Venue:
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Year:
2008

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Abstract

Current processors frequently run applications containing loop structures. However, traditional processor designs do not take into account the semantic information of the executed loops, failing to exploit an important opportunity. In this paper, we take our first step toward a loop-conscious processor architecture that has great potential to achieve high performance and relatively low energy consumption. In particular, we propose to store simple dynamic loops in a buffer, namely the loop window. Loop instructions are kept in the loop window along with all the information needed to build the rename mapping. Therefore, the loop window can directly feed the execution backend queues with instructions, avoiding the need for using the prediction, fetch, decode, and rename stages of the normal processor pipeline. Our results show that the loop window is a worthwhile complexity-effective alternative for processor design that reduces front-end activity by 14% for SPECint benchmarks and by 45% for SPECfp benchmarks.