A program-driven simulation model of an MIMD multiprocessor
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Some Experiments in Local Microcode Compaction for Horizontal Machines
IEEE Transactions on Computers
Scheduling Trees in Parallel/Pipelined Processing Environments
IEEE Transactions on Computers
Extended core storage for the control data 64/6600 systems
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Simulation of an ECS-based operating system
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Observations on high-performance machines
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Toward more efficient computer organizations
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
A new minicomputer/multiprocessor for the ARPA network
AFIPS '73 Proceedings of the June 4-8, 1973, national computer conference and exposition
A pipeline polish string computer
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Pipelining: the generalized concept and sequencing strategies
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Efficiency in generalized pipeline networks
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware
ACM Transactions on Architecture and Code Optimization (TACO)
LPA: a first approach to the loop processor architecture
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Parallelism and Array Processing
IEEE Transactions on Computers
Some computer organizations and their effectiveness
IEEE Transactions on Computers
Static speculation as post-link optimization for the Grid Alu processor
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Improving GPU performance via large warps and two-level warp scheduling
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A case for exploiting subarray-level parallelism (SALP) in DRAM
Proceedings of the 39th Annual International Symposium on Computer Architecture
A shared matrix unit for a chip multi-core processor
Journal of Parallel and Distributed Computing
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About four years ago, in the summer of 1960, Control Data began a project which culminated last month in the delivery of the first 6600 Computer. In 1960 it was apparent that brute force circuit performance and parallel operation were the two main approaches to any advanced computer.