Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
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ACM Transactions on Computer Systems (TOCS)
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ICYCS'93 Proceedings of the third international conference on Young computer scientists
Enhancing instruction level parallelism through compiler-controlled speculation
Enhancing instruction level parallelism through compiler-controlled speculation
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ACM SIGARCH Computer Architecture News
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CC '01 Proceedings of the 10th International Conference on Compiler Construction
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PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
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EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Design of a Computer—The Control Data 6600
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Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
Parallel operation in the control data 6600
AFIPS '64 (Fall, part II) Proceedings of the October 27-29, 1964, fall joint computer conference, part II: very high speed computer systems
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IBM Journal of Research and Development
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
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In this paper we propose and evaluate a post-link-optimization to increase instruction level parallelism by moving instructions from one basic block to the preceding blocks. The Grid Alu Processor used for the evaluations comprises plenty of functional units that are not completely allocated by the original instruction stream. The proposed technique speculatively performs operations in advance by using unallocated functional units. The algorithm moves instructions to multiple predecessors of a source block. If necessary, it adds compensation code to allow the shifted instructions to work on unused registers, whose values will be copied into the original target registers at the time the speculation is resolved. Evaluations of the algorithm show a maximum speedup of factor 2.08 achieved on the Grid Alu Processor compared to the unoptimized version of the same program due to a better exploitation of the ILP and an optimized mapping of loops.