Performance improvement with circuit-level speculation
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Multithreading decoupled architectures for complexity-effective general purpose computing
ACM SIGARCH Computer Architecture News - Special Issue: PACT 2001 workshops
Static speculation as post-link optimization for the Grid Alu processor
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
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In this paper we investigate the complexity of superscalar decode/issue logic assuming primitive gates. We show, assuming that the issuing is performed on the base of opcodes, that the complexity of checking data dependencies is in the order of k3 gates and log k gate delay, k being the issue width, when assuming infinite resources and in-order issuing. In assuming out-of-order issuing the complexities are in the order of 2k gates and log k gate delay, and for out-of-order issuing with renaming in the order of 2k gates and k gate delay. When the resources are restricted we show that the complexity is in the order of nk gates and k2log n delay, n being the cardinality of the instruction set. Finally, by assuming that the issuing is performed using grouping of instructions rather than opcode specific description the complexity is in the order of mk gates and k2logm delay, where m is the number of instruction groups.