A new minicomputer/multiprocessor for the ARPA network

  • Authors:

  • F. E. Heart;S. M. Ornstein;W. R. Crowther;W. B. Barker

  • Affiliations:

  • Bolt Beranek and Newman Inc., Cambridge, Massachusetts;Bolt Beranek and Newman Inc., Cambridge, Massachusetts;Bolt Beranek and Newman Inc., Cambridge, Massachusetts;Bolt Beranek and Newman Inc., Cambridge, Massachusetts

  • Venue:
  • AFIPS '73 Proceedings of the June 4-8, 1973, national computer conference and exposition
  • Year:
  • 1973

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Abstract

Since the early years of the digital computer era, there has been a continuing attempt to gain processing power by organizing hardware processors so as to achieve some form of parallel operation. One important thread has been the use of an array of processors to allow a single control stream to operate simultaneously on a multiplicity of data streams; the most ambitious effort in this direction has been the ILLIAC IV project. Another important thread has been the partitioning of problems so that several control streams can operate in parallel. Often functions have been unloaded from a central processor onto various specialized processors; examples include data channels, display processors, front-end communication processors, on-line data preprocessors---in fact, I/O processors of all sorts. Similarly, dual processor systems have been used to provide load sharing and increased reliability. Still another thread has been the construction of pipeline systems in which sub-pieces of a single (generally large) processor work in parallel on successive phases of a problem. In some of these pipeline approaches the parallelism is "hidden" and the user considers only a single control stream.