AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
D825 - a multiple-computer system for command & control
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
A facility for experimentation in man-machine interaction
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Very high speed serial and serial-parallel computers HITAC 5020 and 5020E
AFIPS '64 (Fall, part I) Proceedings of the October 27-29, 1964, fall joint computer conference, part I
ACM Transactions on Programming Languages and Systems (TOPLAS)
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
A research center for augmenting human intellect
AFIPS '68 (Fall, part I) Proceedings of the December 9-11, 1968, fall joint computer conference, part I
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
A systematic approach to the design of digital bussing structures
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A new minicomputer/multiprocessor for the ARPA network
AFIPS '73 Proceedings of the June 4-8, 1973, national computer conference and exposition
The Organization of High-Speed Memory for Parallel Block Transfer of Data
IEEE Transactions on Computers
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Many computer systems include one or more high transfer rate secondary storage devices in addition to numerous input-output (I/O) devices. When the processors which manage these devices (frequently referred to as I/O controllers or channels), together with the central processing unit (CPU), communicate almost exclusively with a single primary memory, as in the configuration illustrated in Figure 1, the problem of providing these processors with adequate data transfer capability becomes formidable. Ideally, each processor should be able to transfer a datum to or from primary memory at its convenience without regard to the ability of the memory to accept or supply the datum at that particular moment, or the ability of the processor-to-memory transfer path (memory bus) to effect the transfer. Unfortunately, economic and technical considerations dictate that memory systems of the capability implied must be relegated to the role of standards with which more practical systems may be compared. With practical memory systems, the rate at which data can be transferred between processors and primary memory is limited by the transfer capabilities, or bandwidths, of the memory itself and of the memory busses over which the transfers are made. Furthermore, since the memory system is shared by several processors, care must be taken to keep performance from being degraded excessively by interference caused by simultaneous attempts on the part of several processors to utilize a facility, such as a memory bus, which is capable of handling only a single data transfer at any given moment.