A Combinatorial Problem Related to Interleaved Memory Systems
Journal of the ACM (JACM)
Comments on models of multi-processor multi-memory bank computer systems
WSC '74 Proceedings of the 7th conference on Winter simulation - Volume 1
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Markovian models for performance evaluation of multiprocessor, multimemory computer systems
Markovian models for performance evaluation of multiprocessor, multimemory computer systems
Intercommunication of processors and memory
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
A study of interleaved memory systems
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A Simple Probability Model Yielding Performance Bounds for Modular Memory Systems
IEEE Transactions on Computers
Effects of storage contention on system performance
IBM Systems Journal
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Some Performance Issues in Multiprocessor System Design
IEEE Transactions on Computers
Performance of Cross-Bar Multiprocessor Systems
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
Cache system design in the tightly coupled multiprocessor system
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Organization of semiconductor memories for parallel-pipelined processors
IEEE Transactions on Computers - Special issue on parallel processors and processing
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
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Analytic models are developed to evaluate the performance of a multiprocessor computer system. Markov chain techniques are used to model memory conflicts when the memory is modularized. The instruction execution rate (IER) is chosen as the measure of performance. The performance is studied with different storage allocations for instructions and data and with interleaving in the instruction space.