A Survey of Some Theoretical Aspects of Multiprocessing
ACM Computing Surveys (CSUR)
Computer
On the Memory Conflict Problem in Multiprocessor Systems
IEEE Transactions on Computers
An Investigation of Alternative Cache Organizations
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Multiple Microprocessors with Common Main and Control Memories
IEEE Transactions on Computers
On the Performance of Certain Multiprocessor Computer Organizations
IEEE Transactions on Computers
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
Design considerations for a heterogeneous tightly-coupled multiprocessor system
AFIPS '75 Proceedings of the May 19-22, 1975, national computer conference and exposition
Structural aspects of the system/360 model 85: II the cache
IBM Systems Journal
The Combined Effectiveness of Unimodular Transformations, Tiling, and Software Prefetching
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Evaluation of cache consistency algorithm performance
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Exploit temporal locality of shared data in SRC enabled CMP
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Filtering directory lookups in CMPs with write-through caches
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Filtering directory lookups in CMPs
Microprocessors & Microsystems
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Cache is a fast buffer memory between the processor and the main memory and has been extensively used in the larger computer systems. The principle of operation and the various designs of the cache in the uniprocessor system are well documented. The memory system of multiprocessors has also received much attention recently; however, they are limited to the systems without a cache. Little if any information exists in the literature addressing the principle and design considerations of the cache system in the tightly coupled multiprocessor environment. This paper describes such a cache design. System requirements in the multiprocessor environment as well as the cost-performance trade-offs of the cache system design are given in detail. The possibility of sharing the cache system hardware with other multiprocessing facilities (such as dynamic address translation, storage protection, locks, serialization, and the system clocks) is also discussed.