Considerations in block-oriented systems design
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Minerva: An Adaptive Subblock Coherence Protocol for Improved SMP Performance
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
IEEE Transactions on Computers
An Investigation of Alternative Cache Organizations
IEEE Transactions on Computers
Slave Memories and Segmentation
IEEE Transactions on Computers
On the Design of Bayesian Storage Allocation Algorithms for Paging and Segmentation
IEEE Transactions on Computers
Techniques of Program Execution with a Writable Control Memory
IEEE Transactions on Computers
The Memory System of a High-Performance Personal Computer
IEEE Transactions on Computers
Delayed-Staging Hierarchy Optimization
IEEE Transactions on Computers
On the Apparent Continuity of Processing in a Paging Environment
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
Cache system design in the tightly coupled multiprocessor system
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
IEEE Transactions on Computers
Determination of Cache's Capacity and its Matching Storage Hierarchy
IEEE Transactions on Computers
On the Bandwidth and Interference in Interleaved Memory Systems
IEEE Transactions on Computers
Reducing Network-on-Chip energy consumption through spatial locality speculation
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput
Proceedings of the 38th annual international symposium on Computer architecture
Reconstructing hardware transactional memory for workload optimized systems
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
The dynamic granularity memory system
Proceedings of the 39th Annual International Symposium on Computer Architecture
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
A locality-aware memory hierarchy for energy-efficient GPU architectures
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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The cache, a high-speed buffer establishing a storage hierarchy in the Model 85, is discussed in depth in this part, since it represents the basic organizational departure from other SYSTEM/360 computers. Discussed are organization and operation of the cache, including the mechanisms used to locate and retrieve data needed by the processor. The internal performance studies that led to use of the cache are described, and simulated performance of the chosen configuration is compared with that of a theoretical system having an entire 80-nanosecond main storage. Finally, the effects of varying cache parameters are discussed and tabulated.