Algorithms for Parallel-Search Memories
Journal of the ACM (JACM)
A use of fast and slow memories in list-processing languages
Communications of the ACM
Dynamic storage allocation in the Atlas computer, including an automatic use of a backing store
Communications of the ACM
Cellular Interconnection Arrays
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
Parallel computing with vertical data
IRE-AIEE-ACM '60 (Eastern) Papers presented at the December 13-15, 1960, eastern joint IRE-AIEE-ACM computer conference
ASP: a new concept in language and machine organization
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Associative processing for general purpose computers through the use of modified memories
AFIPS '68 (Fall, part II) Proceedings of the December 9-11, 1968, fall joint computer conference, part II
Structural aspects of the system/360 model 85: II the cache
IBM Systems Journal
Hierarchical processors-and-memory architecture for high performance computing
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
IEEE Transactions on Computers
A combined arithmetic logic unit and memory element for the design of a parallel computer
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
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If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.