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Proceedings of the 1990 ACM/IEEE conference on Supercomputing
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Journal of Parallel and Distributed Computing
Surround-screen projection-based virtual reality: the design and implementation of the CAVE
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Enabling technologies for petaflops computing
Enabling technologies for petaflops computing
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
The memory wall and the CMOS end-point
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Missing the memory wall: the case for processor/memory integration
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Heterogeneous computing machines and Amdahl's law
Parallel Computing
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The Science of Virtual Reality and Virtual Environments
Automatic Detection of Parallelism: A Grand Challenge for High-Performance Computing
IEEE Parallel & Distributed Technology: Systems & Technology
Benchmarking with Real Industrial Applications: The SPEC High-Performance Group
IEEE Computational Science & Engineering
A Heterogeneous Hierarchical Solution to Cost-efficient High Performance Computing
SPDP '96 Proceedings of the 8th IEEE Symposium on Parallel and Distributed Processing (SPDP '96)
EXECUBE-A New Architecture for Scaleable MPPs
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
IEEE Transactions on Computers
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Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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This paper outlines a cost-effective multiprocessor architecture that takes into consideration the importance of hardware and software costs as well as delivered performance in the context of real applications. The proposed architecture, HPAM, is organized as a hierarchy of processors-and-memory subsystems. Each subsystem contains a homogeneous parallel machine. Across the levels of the hierarchy, processor speeds and interconnection technology vary. The HPAM design is driven by several considerations: the observed characteristics of real applications, cost-efficiency considerations and the need for ease-of-usage. Rationales and the results of a preliminary study that motivated the design of this architecture are presented. These results include benchmark data that expose the advantages of HPAM over other architectures. Technology trends that support the desirability and viability of the proposed machine organization are also presented. Two classes of applications that demand 100 Teraops computation rates and that will drive future HPAM work are discussed. Furthermore a flexible software environment is proposed for this architecture, which facilitates several programming scenarios: automatic program translation, library based programming and performance-guided coding by expert programmers.