Improving the Performance of Heterogeneous DSMs via Multithreading
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Hierarchical processors-and-memory architecture for high performance computing
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
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IEEE Transactions on Parallel and Distributed Systems
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Two facts that suggest the desirability of a hierarchical approach to cost-effective high-performance computing are empirically established in this paper. The first fact is the temporal locality of programs with respect to the degree of parallelism. Two temporal (instruction and data) locality principles are identified and empirically established for a set of programs. The impact of this behavior is discussed with respect to the proposed heterogeneous multilevel architecture. The second fact that supports the hierarchical architecture is the cost-efficiency advantage of heterogeneous over homogeneous multiprocessor systems. An initial performance analysis is presented which quantifies this fact for the proposed heterogeneous hierarchical organization. The proposed multilevel processor configuration uses fast and costly resources sparingly to reduce sequential and low parallelism bottlenecks. The resulting organization tries to balance cost, speed and parallelism granularity.