Processor coupling: integrating compile time and runtime scheduling for parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Mosaic C: An Experimental Fine-Grain Multicomputer
Proceedings of the International Conference on Future Tendencies in Computer Science, Control and Applied Mathematics
Parallel Image Correlation: Case Study to Examine Trade-Offs in Algorithm-to-Machine Mappings
The Journal of Supercomputing
Journal of Electronic Testing: Theory and Applications
An Effective Memory--Processor Integrated Architecture for Computer Vision
ICPP '97 Proceedings of the international Conference on Parallel Processing
Background Compensation and an Active-Camera Motion Tracking Algorithm
ICPP '97 Proceedings of the international Conference on Parallel Processing
Combined DRAM and logic chip for massively parallel systems
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
The Illinois Aggressive Coma Multiprocessor project (I-ACOMA)
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Pursuing a Petaflop: Point Designs for 100 TF Computers Using PIM Technologies
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Morphological image processing on three parallel machines
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Architecture, algorithms and applications for future generation supercomputers
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Hierarchical processors-and-memory architecture for high performance computing
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Employing Logic-Enhanced Memory for High-performance ATM Network Interfaces
HPDC '96 Proceedings of the 5th IEEE International Symposium on High Performance Distributed Computing
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Hiding Communication Latency in Data Parallel Applications
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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The EXECUBE chip is a new single part type building block for MPP systems that scales seamlessly from a few chips (with a few hundred mips) to thousands of chips with petaop potential. Further, the chip architecture supports directly both SIMD and MIMD modes of processing, permitting not only the best of both current parallel computing modes but also new modes not possible with more conventional designs. This paper discusses the overall architecture of the EXECUBE chip, the new computational model it represents, some comparisons against the current state of the art, how it might be used for real applications, and some extrapolations into future developments.