Hypernet: A communication-efficient architecture for constructing massively parallel computers
IEEE Transactions on Computers
Mapping neural networks onto message-passing multicomputers
Journal of Parallel and Distributed Computing - Neural Computing
Parallel processing for super-computers and artificial intelligence
Parallel processing for super-computers and artificial intelligence
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Communication-efficient interconnection networks for parallel computations
Communication-efficient interconnection networks for parallel computations
Theoretical aspects of VLSI pin limitations
SIAM Journal on Computing
IEEE Transactions on Parallel and Distributed Systems
Broadcasting algorithms for the star-connected cycles interconnection network
Journal of Parallel and Distributed Computing
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Bused Hypercubes and Other Pin-Optimal Networks
IEEE Transactions on Parallel and Distributed Systems
Algorithms and Properties of a New Two-Level Network with Folded Hypercubes as Basic Modules
IEEE Transactions on Parallel and Distributed Systems
Robust shearsort on incomplete bypass meshes
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Periodically regular chordal ring networks for massively parallel architectures
FRONTIERS '95 Proceedings of the Fifth Symposium on the Frontiers of Massively Parallel Computation (Frontiers'95)
SPDP '96 Proceedings of the 8th IEEE Symposium on Parallel and Distributed Processing (SPDP '96)
The Star Connected Cycles: A Fixed-Degree Network For Parallel Processing
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
EXECUBE-A New Architecture for Scaleable MPPs
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
The SegBus platform - architecture and communication mechanisms
Journal of Systems Architecture: the EUROMICRO Journal
Local search: is brute-force avoidable?
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
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Inter-module bandwidth is one of the major constraints on the performance of current and future parallel systems. In this paper, we propose and evaluate several high-performance bus-based parallel architectures, including bus-based cyclic networks (BCNs) and quotient cyclic networks (BQCNs), which are particularly efficient in view of their respective inter-module communication patterns. The inter-cluster connection in a BCN is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degree of a basic BCN is 3; while those of BQCNs and enhanced BCNs can vary from a small constant (e.g., 2) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. A variety of algorithms can be performed efficiently on these networks, thus proving the versatility of BCNs and BQCNs.