Digital systems engineering
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Round-robin arbiter design and generation
Proceedings of the 15th international symposium on System Synthesis
Design theory and implementation for low-power segmented bus systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Asynchronous Macrocell Interconnect using MARBLE
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Networks on chip
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Multicomputer System with Dynamic Architecture
IEEE Transactions on Computers
Implementation of a self-timed segmented bus
IEEE Design & Test
Local search: is brute-force avoidable?
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
Service based communication for MPSoC platform-SegBus
Microprocessors & Microsystems
A development and verification framework for the SegBus platform
Journal of Systems Architecture: the EUROMICRO Journal
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In this study, we introduce the SegBus architecture, a synchronous segmented bus platform for systems on chip. We present the envisioned structure in detail, and also address aspects of communication on the platform. The motivation behind SegBus is the search for performance improvements, in several directions, such as global throughput, power consumption, modularity, adaptability. By means of an example, we illustrate the capabilities of the described architecture. The implementation strategy targets FPGA technology, and allows for the utilization of multiple clock domains. The platform emerges as a highly design-time configurable system, adaptable to various design constraints.