The SegBus platform - architecture and communication mechanisms
Journal of Systems Architecture: the EUROMICRO Journal
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
Distribution of Programs for a System with Dynamic Architecture
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
Problems of Designing Supersystems with Dynamic Architectures
IEEE Transactions on Computers
Adaptable pipeline system with dynamic architecture
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Architectures for supersystems of the '80s
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
A distributed operating system for a powerful system with dynamic architecture
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Reconfigurable multicomputer networks for very fast real-time applications
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
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This paper considers the organization of certain multicomputer systems with a particular type of dynamic architecture. The system allows one to reconfigure via software available hardware resources (widths of processors, memories, and I/O units), forming computers with different word sizes. A multicomputer system is formed from identical dynamic computer groups. Each group may assume a variety of architectural states which are distinct from each other by the number and sizes of concurrent computers. To construct one dynamic computer group, one uses a universal building module, an 8-bit microprocessor on an LSI chip, and standard memory units. This paper considers basic principles of dynamic computer group implementation: organization of parallel (for words) and serial (for instructions) exchange between primary memory and processor, automatic variation of the time intervals assigned for operations which are executed in differently sized computers, formation of the processor with variable word size, switching from one architectural state to another, scheduling of the memory, and task synchronization.