The shuffle/exchange-plus networks
ACM-SE 20 Proceedings of the 20th annual Southeast regional conference
Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Microprocessor implementation of a parallel processor
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Interprocessor connections--capabilities, exploitation and effectiveness.
Interprocessor connections--capabilities, exploitation and effectiveness.
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
Design of a Massively Parallel Processor
IEEE Transactions on Computers
Interference Analysis of Shuffle/Exchange Networks
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Fault-Diagnosis for a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
A Multicomputer System with Dynamic Architecture
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Design and implementation of the banyan interconnection network in TRAC
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Determining an Optimal Secondary Storage Service Rate for the PASM Control System
IEEE Transactions on Computers
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
IEEE Transactions on Computers - The MIT Press scientific computation series
A connecting network with fault tolerance capabilities
IEEE Transactions on Computers - The MIT Press scientific computation series
The Load-Sharing Banyan Network
IEEE Transactions on Computers
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Flexible oblivious router architecture
IBM Journal of Research and Development
Reliability Bounds for Large Multistage Interconnection Networks
PARA '02 Proceedings of the 6th International Conference on Applied Parallel Computing Advanced Scientific Computing
Space Division Architectures for Crosstalk Reduction in Optical Interconnection Networks
QoS-IP 2003 Proceedings of the Second International Workshop on Quality of Service in Multiservice IP Networks
Performance analysis and fault tolerance of randomized routing on Clos networks
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Analysis of a multistage interconnection network using binary decision diagrams (BDD)
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Design and Evaluation of a Fault-Tolerant Multiprocessor Using Hardware Recovery Blocks
IEEE Transactions on Computers
IEEE Transactions on Computers
Task Preloading Schemes for Reconfigurable Parallel Processing Systems
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
A Class of Redundant Path Multistage Interconnection Networks
IEEE Transactions on Computers
Performance and reliability analysis of new fault-tolerant advance omega network
WSEAS Transactions on Computers
A new min: fault-tolerant advance omega network
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Journal of Computer Systems, Networks, and Communications
Modified composite Banyan network with an enhanced terminal reliability
Computer Communications
A fault-tolerant 2*2 switching element for switching networks
Computer Communications
Fault tolerance design for large-scale optical switches
Optical Switching and Networking
F10: a fault-tolerant engineered network
nsdi'13 Proceedings of the 10th USENIX conference on Networked Systems Design and Implementation
| Hi-index | 15.01 |
The Extra Stage Cube (ESC) interconnection network, a fault-tolerant structure, is proposed for use in large-scale parallel and distributed supercomputer systems. It has all of the interconnecting capabilities of the multistage cube-type networks that have been proposed for many supersystems. The ESC is derived from the Generalized Cube network by the addition of one stage of interchange boxes and a bypass capability for two stages. It is shown that the ESC provides fault tolerance for any single failure. Further, the network can be controlled even when it has a failure, using a simple modification of a routing tag scheme proposed for the Generalized Cube. Both one-to-one and broadcast connections under routing tag control are performable by the faulted ESC. The ability of the ESC to operate with multiple faults is examined. The ways in which the ESC can be partitioned and permute data are described.