Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Complexity issues in VLSI: optimal layouts for the shuffle-exchange graph and other networks
Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
A Group-Theoretic Model for Symmetric Interconnection Networks
IEEE Transactions on Computers
Stretching a Knock-Knee Layout for Multilayer Wiring
IEEE Transactions on Computers
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Static and dynamic communication in parallel computing
Static and dynamic communication in parallel computing
RH: A Versatile Family of Reduced Hypercube Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements
IEEE Transactions on Parallel and Distributed Systems
Hierarchical hypercube networks (HHN) for massively parallel computers
Journal of Parallel and Distributed Computing
Efficient VLSI Layouts for Homogeneous Product Networks
IEEE Transactions on Computers
Layout of the batcher bitonic sorter (extended abstract)
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Macro-Star Networks: Efficient Low-Degree Alternatives to Star Graphs
IEEE Transactions on Parallel and Distributed Systems
Compact grid layouts of multi-level networks
STOC '99 Proceedings of the thirty-first annual ACM symposium on Theory of computing
VLSI layouts of complete graphs and star graphs
Information Processing Letters
Some compact layouts of the butterfly
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
Tighter Layouts of the Cube-Connected Cycles
IEEE Transactions on Parallel and Distributed Systems
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Transposition Networks as a Class of Fault-Tolerant Robust Networks
IEEE Transactions on Computers
Products of Networks with Logarithmic Diameter and Fixed Degree
IEEE Transactions on Parallel and Distributed Systems
The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks
IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
VLSI Architecture: Past, Present, and Future
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Efficient VLSI Layouts of Hypercubic Networks
FRONTIERS '99 Proceedings of the The 7th Symposium on the Frontiers of Massively Parallel Computation
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The Index-Permutation Graph Model for Hierarchical Interconnection Networks
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
A complexity theory for VLSI
Efficient low-degree interconnection networks for parallel processing: topologies, algorithms, vlsi layouts, and fault tolerance
Computational Aspects of VLSI
The Star Connected Cycles: A Fixed-Degree Network For Parallel Processing
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
AT2L2 o N2/2 for fast fourier transform in multilayer VLSI
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Off-chip communication architectures for high throughput network processors
Computer Communications
Layout volumes of the hypercube
GD'04 Proceedings of the 12th international conference on Graph Drawing
| Hi-index | 0.00 |
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-layer model, the layout area for a variety of networks can be reduced by a factor of about (L/2)2 compared to the layout area required under a 2-layer model, and the volume and maximum wire length can be reduced by a factor of about L/2, leading to considerably lower cost and/or higher performance. The proposed layouts for k-ary n-cubes, hypercubes, butterfly networks, cube-connected cycles (CCC), folded hypercubes, generalized hypercubes, k-ary n-cube cluster-c, hierarchical hypercube networks, reduced hyper-cubes, hierarchical swap networks, and indirect swap net-works, are the best layouts reported for these networks thus far and are optimal within a small constant factor under both the Thompson model and the multilayer grid model. All of our layouts are optimally scalable in that we can allow each network node to occupy the largest possible area (e.g., o(N/L2) for hypercubes) without increasing the leading constant of the layout area, volume, or maximum wire length.