VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
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We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchical networks. In particular, we construct optimal VLSI layouts for butterfly networks, generalized hypercubes, and star graphs that have areas within a factor of 1 +o(1) from their lower bounds. We also derive efficient layouts for a number of other important networks, such as cube-connected cycles (CCC) and hypernets, which are the best results reported for these networks thus far.